Research Exchange: Designing Energy-Efficient Integrated Circuits and Systems

Designing Energy-Efficient Integrated Circuits and Systems

Lecture: Research Exchange | December 1 | 12-1 p.m. | Sutardja Dai Hall, Banatao Aud., 3rd floor

Elad Alon, Asst. Professor of EECS, UC Berkeley

CITRIS (Ctr for Info Technology Research in the Interest of Society)

Live broadcast at mms://; Questions can be sent via Yahoo IM to username: citrisevents. The schedule for the fall Research Exchange is at


As traditional CMOS technology scaling has essentially ended, electronic systems can no longer simply increase functionality or performance without dissipating more power. In order to surmount this challenge and enable many emerging applications, integrated circuit designers must turn their attention to energy efficiency as their primary driver.

While substantial improvements in energy-efficiency in specific applications are still achievable with today’s CMOS transistors – as I will briefly highlight through our research on 60GHz wireless transceivers – the biggest opportunites for energy reduction in general purpose digital processing may lie in alternative device technologies. In this context, it is important to note that parallel or multi-core processing has emerged as the principal means to increase throughput under a power budget. However, CMOS digital logic gates must dissipate a well-defined minimum energy for each operation they perform, and therefore parallelism alone will eventually cease to be effective.

The cause of the energy limit in CMOS is the fact that the transistors require a relatively large voltage swing in order to achieve sufficient on-to off-current ratio. In contrast, electro-mechanical relays can achieve nearly zero leakage and sub-1mV switching between off- and on-states, and hence may someday enable continued parallelization and orders-of-magnitude improvement in energy efficiency. Achieving this goal requires tailoring the circuits to the characteristics of the relays, and therefore I will describe electro-mechanical relay-optimized circuit architectures.

Furthermore, I will show how these circuit-level insights have enabled substantial recent progress in the realization and reliability of the relays themselves., 510-643-4866

Coming Soon. Event will be webcast live and then put on youtube: