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Post-CMOS Strategy and Carbon Nanoelectronics, Aug 26

Information Technology (IT) industries currently have more than $200 billion in global sales and account for 30% of U.S. GDP and 50% of US economic growth. The unprecedented growth of the IT industry has largely been driven by the nonstop exponential increase in the performance of the CMOS-FET per unit area/dollar, which is enabled by the ability to continue scaling down CMOS transistor sizes and increasing functionality.

However, industry’s ability to scale transistors has become limited recently due to increasing leakage power and inability to reduce switching energy. Unavoidably, the fundamental limitations destine CMOS scaling to a conclusion at around 5-10 nm in 2020.

As CMOS shrinks closer to the point where it can’t get any smaller, an innovative new device and its architecture for the future logic switch becomes very urgent.

The post-CMOS device should show significant advantages in power, performance, density, and cost to enable the extension of the historical cost and performance trends for information technology. Amongst many promising options, the graphene device based on the unique electron transport characteristics has attracted a lot of attention due to their superior electrical and mechanical properties. Logic device based on graphene will have to be built on a new concept, one that takes advantage of the material’s unique properties in a revolutionary architecture.

Moreover, if this new switch can be simultaneously dynamically reconfigured to perform multifunction logic operations must be very attractive.