In nanometer scale CMOS technologies, static power consumption will be the major component of the overall power consumption. Static power has been rapidly growing as technologies have scaled supply voltage VDD and threshold voltage Vth down to maintain drive current and reduce dynamic power consumption, at the cost of an exponential increase in transistor leakage currents. Static power can be as much as 20% of the power budget of current high-end microprocessors, and this will likely increase as future technologies continue to reduce Vth. Multiple threshold voltage processes are becoming increasingly popular as a way to maintain performance while reducing total power consumption. A low transistor threshold voltage may be used on critical paths to meet timing constraints. Paths with timing slack may be assigned a higher threshold voltage to reduce the subthreshold leakage component of static power consumption. Multiple supply voltages can be similarly used to further reduce power consumption while maintaining performance. Implementing a design in a multi-VDD technology requires level converters that restore a low supply voltage signal to a high input voltage for high supply voltage gates: a low VDD input to a high VDD static CMOS gate applies a forward bias to the PMOS transistor causing unacceptably large static currents. Asynchronous level converters allow low-VDD to high-VDD transitions anywhere in the circuit, leading to a larger flexibility in circuit partitioning. Synchronous level converters, on the other hand, combine the level converter with a register. In our research we examined a variety of new circuits for asynchronous level converters that show promising results, reducing the power and performance overhead for asynchronous level conversion, and robustness to supply voltage noise. In order to utilize process and circuit technologies supporting multiple supply and threshold voltages, CAD tools are needed to assign supply voltages to gates and threshold voltages to transistors in a way that minimizes power. Supply and threshold voltage assignment optimization should ideally be done in conjunction with transistor sizing. Algorithmic work within both research groups has focused on optimizing combinational circuitry with synchronous level converters at the peripheries. Extensions of these approaches will incorporate asynchronous level converters. We have examined several algorithmic approaches. We use gate delay and power models based on posynomial functions. With posynomial models, the combinational VDD, Vth and sizing problem is convex with a global optimum that can be determined by geometric programming. Geometric programming results on small benchmarks indicate up to 22% total power savings using multiple supply and threshold voltages, compared with optimally assigning a single global supply voltage and threshold voltages. Dynamic programming and linear programming slack assignment heuristics for threshold voltage assignment and sizing have been implemented using timing models based on logical effort. Dual threshold voltages in combination with sizing show 25-55% power savings compared to sizing only for the ISCAS'85 combinational benchmarks. We are currently working to extend these approaches to handle more accurate gate delay models, and improve the run time.